Seminars Archive

Readout architecture of the pixel demonstrator Front End chip for the ATLAS pixel tracker

Abstract
Large advances have been made over the last two years in the development of the Front End readout electronics for the ATLAS Pixel Tracker. It will be described here and an overview of two architecture concepts, a radiation soft and radiation hard technology, of the readout chip for pixel detector arrays will be given. The circuits are characterized by a low power, sparse scan, readout architecture. This architecture supports an analog Front End capable to extract the time over threshold (ToT) information from signals produced inside a bump-bonded pixel detector. The ToT information along with a 2-D spatial address are filtered by a trigger unit, selecting the hits to be read out. The selected events are then transmitted over a 40 MHz serial data link. Moreover, some performance results of the circuits will be presented.